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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-15 19:00:34 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-15 19:00:34 -0800 |
| commit | 6d4b6b1e69b2e332d512ed151398bb6bd8e3f3c7 (patch) | |
| tree | 27bf282d1f7773c516d8a9d393efdbc5bb4a001f /frontends/verilog/preproc.cc | |
| parent | b0231df3e5c79c553faed93e3e7af798511a1e28 (diff) | |
| parent | e9dc2759c414bdc8ab663fd5c8350b40b099b456 (diff) | |
| download | yosys-6d4b6b1e69b2e332d512ed151398bb6bd8e3f3c7.tar.gz yosys-6d4b6b1e69b2e332d512ed151398bb6bd8e3f3c7.tar.bz2 yosys-6d4b6b1e69b2e332d512ed151398bb6bd8e3f3c7.zip | |
Merge pull request #1575 from rodrigomelo9/master
Fixed some missing "verilog_" in documentation
Diffstat (limited to 'frontends/verilog/preproc.cc')
| -rw-r--r-- | frontends/verilog/preproc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7e107dc26..161253a99 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -28,7 +28,7 @@ * * Ad-hoc implementation of a Verilog preprocessor. The directives `define, * `include, `ifdef, `ifndef, `else and `endif are handled here. All other - * directives are handled by the lexer (see lexer.l). + * directives are handled by the lexer (see verilog_lexer.l). * */ |