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| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-11-21 13:05:30 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-01-29 01:40:00 +0100 |
| commit | 7e0e42f907260e76e3c7cb01c907a0cf61a6e326 (patch) | |
| tree | 1a948b1efc41c7d639feff064eb9e8713c2486eb /frontends/verilog/preproc.cc | |
| parent | 7939727d14f44b5d56ca3806d0907e9fceea2882 (diff) | |
| download | yosys-7e0e42f907260e76e3c7cb01c907a0cf61a6e326.tar.gz yosys-7e0e42f907260e76e3c7cb01c907a0cf61a6e326.tar.bz2 yosys-7e0e42f907260e76e3c7cb01c907a0cf61a6e326.zip | |
xilinx: Add simulation model for DSP48 (Virtex 4).
Diffstat (limited to 'frontends/verilog/preproc.cc')
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