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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-24 18:30:51 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-24 18:30:51 -0700 |
| commit | 822d0b7789fdfe94bfe11b96546af8430e5f3299 (patch) | |
| tree | edd245e4d9f1cb2e072357e4240c5290fe4f3f01 /frontends/verilog/preproc.cc | |
| parent | f0c6b73b72b4ddc2b60865bcbd8934eba1bb6f52 (diff) | |
| download | yosys-822d0b7789fdfe94bfe11b96546af8430e5f3299.tar.gz yosys-822d0b7789fdfe94bfe11b96546af8430e5f3299.tar.bz2 yosys-822d0b7789fdfe94bfe11b96546af8430e5f3299.zip | |
opt_rmdff to optimise even in presence of enable signal, even removing
Diffstat (limited to 'frontends/verilog/preproc.cc')
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