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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-21 09:52:21 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-21 09:52:21 +0100 |
| commit | 8f610dca580b3f33064382fccd4f66152e6ea50f (patch) | |
| tree | c5890e0b3f9d7abc7a3bf0ee6f947f25b42c7856 /frontends/verilog/preproc.cc | |
| parent | 87c771756661fda7dbcdd0bd1bf41af0c818e0d7 (diff) | |
| download | yosys-8f610dca580b3f33064382fccd4f66152e6ea50f.tar.gz yosys-8f610dca580b3f33064382fccd4f66152e6ea50f.tar.bz2 yosys-8f610dca580b3f33064382fccd4f66152e6ea50f.zip | |
Added -S option for simple synthesis to gate logic
Diffstat (limited to 'frontends/verilog/preproc.cc')
0 files changed, 0 insertions, 0 deletions