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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 10:29:40 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 10:29:40 -0800 |
| commit | 94f15f023c8720d84211ac75980cf0b0f492411d (patch) | |
| tree | 29f40490883b15fec68ef6aba99767a0deaecc4f /frontends/verilog/preproc.cc | |
| parent | 76ba06a79ea917a0e515aa0e99ae41f42e8bddc9 (diff) | |
| parent | f52c6efd9da161e625538f9e8c23875efebda60f (diff) | |
| download | yosys-94f15f023c8720d84211ac75980cf0b0f492411d.tar.gz yosys-94f15f023c8720d84211ac75980cf0b0f492411d.tar.bz2 yosys-94f15f023c8720d84211ac75980cf0b0f492411d.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'frontends/verilog/preproc.cc')
| -rw-r--r-- | frontends/verilog/preproc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7e107dc26..161253a99 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -28,7 +28,7 @@ * * Ad-hoc implementation of a Verilog preprocessor. The directives `define, * `include, `ifdef, `ifndef, `else and `endif are handled here. All other - * directives are handled by the lexer (see lexer.l). + * directives are handled by the lexer (see verilog_lexer.l). * */ |