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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-05 06:49:06 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-05 06:49:06 -0700 |
| commit | 99aff5a0f9f322bf4498fe06094de9919ed56681 (patch) | |
| tree | 7115f9042aa94798283a091633b760ad56e6769f /frontends/verilog/preproc.cc | |
| parent | 584780d776c92bc91731dbc2710dd8d9a624dc70 (diff) | |
| parent | eb5eb60fd4af431ea38a50ad1deebcc40ad4c222 (diff) | |
| download | yosys-99aff5a0f9f322bf4498fe06094de9919ed56681.tar.gz yosys-99aff5a0f9f322bf4498fe06094de9919ed56681.tar.bz2 yosys-99aff5a0f9f322bf4498fe06094de9919ed56681.zip | |
Merge pull request #2023 from YosysHQ/eddie/specify_src
verilog: fix specify src attribute
Diffstat (limited to 'frontends/verilog/preproc.cc')
0 files changed, 0 insertions, 0 deletions