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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 11:44:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 11:44:00 -0700 |
| commit | e6b55e8b38d98e28ee53f7b470cef1bcc3b399f3 (patch) | |
| tree | e0a5854f4af16f8fa091c7f0fcd7695756fdea61 /frontends/verilog/preproc.cc | |
| parent | 584780d776c92bc91731dbc2710dd8d9a624dc70 (diff) | |
| download | yosys-e6b55e8b38d98e28ee53f7b470cef1bcc3b399f3.tar.gz yosys-e6b55e8b38d98e28ee53f7b470cef1bcc3b399f3.tar.bz2 yosys-e6b55e8b38d98e28ee53f7b470cef1bcc3b399f3.zip | |
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
Diffstat (limited to 'frontends/verilog/preproc.cc')
0 files changed, 0 insertions, 0 deletions