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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 10:22:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 10:22:05 -0700 |
| commit | eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37 (patch) | |
| tree | 2f7baee8ade49e326f002d3fd799f95891ff95e0 /frontends/verilog/preproc.cc | |
| parent | ad8e7878f6321b9c35ae41b651a7da9a733ce4be (diff) | |
| download | yosys-eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37.tar.gz yosys-eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37.tar.bz2 yosys-eca9fc01a78c5cc4c1d8120e2ccdf18211bcef37.zip | |
verilog: set src attribute for primitives
Diffstat (limited to 'frontends/verilog/preproc.cc')
0 files changed, 0 insertions, 0 deletions