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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-20 12:54:10 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-11-20 12:54:10 +0100 |
| commit | f6ff311a1dc9876911594328350e2d3fc62a5535 (patch) | |
| tree | a1a5aa06a6c361222c3a880c408b2d31ab691818 /frontends/verilog/preproc.cc | |
| parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
| download | yosys-f6ff311a1dc9876911594328350e2d3fc62a5535.tar.gz yosys-f6ff311a1dc9876911594328350e2d3fc62a5535.tar.bz2 yosys-f6ff311a1dc9876911594328350e2d3fc62a5535.zip | |
Do not rename VHDL entities to "entity(impl)" when they are top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog/preproc.cc')
0 files changed, 0 insertions, 0 deletions