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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-10-21 05:42:47 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-10-21 05:42:47 +0200 |
| commit | 16a177560f27c77ba490ac7dbe9eae3d3766ca1e (patch) | |
| tree | 6a82253e2ce91d5a03b34ade1e8016e249c11e45 /frontends/verilog/preproc.h | |
| parent | e64456f92025c26f8b66e77901f78eca726d856a (diff) | |
| download | yosys-16a177560f27c77ba490ac7dbe9eae3d3766ca1e.tar.gz yosys-16a177560f27c77ba490ac7dbe9eae3d3766ca1e.tar.bz2 yosys-16a177560f27c77ba490ac7dbe9eae3d3766ca1e.zip | |
Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'frontends/verilog/preproc.h')
0 files changed, 0 insertions, 0 deletions