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| author | Claire Xen <claire@clairexen.net> | 2022-02-11 16:03:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-11 16:03:12 +0100 |
| commit | 49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch) | |
| tree | d0f20b8def36e551c6735d4fc6033aaa2633fe80 /frontends/verilog/preproc.h | |
| parent | 90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff) | |
| parent | e0165188669fcef2c5784c9916683889a2164e5d (diff) | |
| download | yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.gz yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.bz2 yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.zip | |
Merge branch 'master' into clk2ff-better-names
Diffstat (limited to 'frontends/verilog/preproc.h')
| -rw-r--r-- | frontends/verilog/preproc.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.h b/frontends/verilog/preproc.h index 673d633c0..330855a92 100644 --- a/frontends/verilog/preproc.h +++ b/frontends/verilog/preproc.h @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -42,6 +42,7 @@ struct define_map_t // Add a definition, overwriting any existing definition for name. void add(const std::string &name, const std::string &txt, const arg_map_t *args = nullptr); + void add(const std::string &name, const define_body_t &body); // Merge in another map of definitions (which take precedence // over anything currently defined). |