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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-22 18:09:10 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-22 18:09:10 +0200 |
| commit | 2c8c8b3c74ccc630e56c412a83fa60fb7066fb4d (patch) | |
| tree | 95a650ffaadbce982b0801ef0e782e1f193992cc /frontends/verilog/verilog_frontend.cc | |
| parent | 4c449caf9bb7a855b8e61cb96f99f59141ea6ef5 (diff) | |
| parent | 4a32e29445f65edd1726808a7353a9d0e2560c00 (diff) | |
| download | yosys-2c8c8b3c74ccc630e56c412a83fa60fb7066fb4d.tar.gz yosys-2c8c8b3c74ccc630e56c412a83fa60fb7066fb4d.tar.bz2 yosys-2c8c8b3c74ccc630e56c412a83fa60fb7066fb4d.zip | |
Merge pull request #1289 from mmicko/anlogic_fixes
Anlogic fixes and optimization
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
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