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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-19 19:49:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-19 19:49:14 +0200 |
| commit | 4214561890c4d25d8a172ea7d8b8201f800b3c90 (patch) | |
| tree | ac56708adda22debe4714e9017339157ee77a9d7 /frontends/verilog/verilog_frontend.cc | |
| parent | a860efa8ac37dfe20cd74324dd02136082aa2c1c (diff) | |
| download | yosys-4214561890c4d25d8a172ea7d8b8201f800b3c90.tar.gz yosys-4214561890c4d25d8a172ea7d8b8201f800b3c90.tar.bz2 yosys-4214561890c4d25d8a172ea7d8b8201f800b3c90.zip | |
Improved ast dumping (ast/verilog frontend)
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 1311c3c3a..9c6a5b64e 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -49,11 +49,11 @@ struct VerilogFrontend : public Frontend { log("Load modules from a verilog file to the current design. A large subset of\n"); log("Verilog-2005 is supported.\n"); log("\n"); - log(" -dump_ast\n"); - log(" dump abstract syntax tree (after simplification)\n"); + log(" -dump_ast1\n"); + log(" dump abstract syntax tree (before simplification)\n"); log("\n"); - log(" -dump_ast_diff\n"); - log(" dump ast differences before and after simplification\n"); + log(" -dump_ast2\n"); + log(" dump abstract syntax tree (after simplification)\n"); log("\n"); log(" -dump_vlog\n"); log(" dump ast as verilog code (after simplification)\n"); @@ -103,8 +103,8 @@ struct VerilogFrontend : public Frontend { } virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) { - bool flag_dump_ast = false; - bool flag_dump_ast_diff = false; + bool flag_dump_ast1 = false; + bool flag_dump_ast2 = false; bool flag_dump_vlog = false; bool flag_nolatches = false; bool flag_nomem2reg = false; @@ -121,13 +121,12 @@ struct VerilogFrontend : public Frontend { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; - if (arg == "-dump_ast") { - flag_dump_ast = true; + if (arg == "-dump_ast1") { + flag_dump_ast1 = true; continue; } - if (arg == "-dump_ast_diff") { - flag_dump_ast = true; - flag_dump_ast_diff = true; + if (arg == "-dump_ast2") { + flag_dump_ast2 = true; continue; } if (arg == "-dump_vlog") { @@ -205,7 +204,7 @@ struct VerilogFrontend : public Frontend { frontend_verilog_yyparse(); frontend_verilog_yylex_destroy(); - AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt); + AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt); if (!flag_nopp) fclose(fp); |