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| author | Sahand Kashani <sahand.kashani@gmail.com> | 2020-03-24 21:07:08 +0100 |
|---|---|---|
| committer | Sahand Kashani <sahand.kashani@gmail.com> | 2020-03-24 21:07:08 +0100 |
| commit | 6c2b220af56ccac5ce343914cab095114656c83a (patch) | |
| tree | e64a80761d243ded94c9a19fbc724a796a61dd87 /frontends/verilog/verilog_frontend.cc | |
| parent | 018116e478259f175a0a239da52bbbca8fa69b22 (diff) | |
| download | yosys-6c2b220af56ccac5ce343914cab095114656c83a.tar.gz yosys-6c2b220af56ccac5ce343914cab095114656c83a.tar.bz2 yosys-6c2b220af56ccac5ce343914cab095114656c83a.zip | |
Remove use of auto for simple types + simplify src attribute computation
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
0 files changed, 0 insertions, 0 deletions