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| author | Clifford Wolf <clifford@clifford.at> | 2017-12-19 21:44:05 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-12-19 21:44:05 +0100 |
| commit | b66d50e62d0dcd2b495c360fa64f3c7b4017b842 (patch) | |
| tree | 73fda0399de75547096c5d3ecac08f9ac4a47bc4 /frontends/verilog/verilog_frontend.cc | |
| parent | 292984896b417a50b1597a1e3a66de53bab0f13e (diff) | |
| download | yosys-b66d50e62d0dcd2b495c360fa64f3c7b4017b842.tar.gz yosys-b66d50e62d0dcd2b495c360fa64f3c7b4017b842.tar.bz2 yosys-b66d50e62d0dcd2b495c360fa64f3c7b4017b842.zip | |
Fix minor typo in "prep" help message
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
0 files changed, 0 insertions, 0 deletions