diff options
| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-11 17:08:40 +0100 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-11 17:08:40 +0100 |
| commit | ec3faa7b967564dabdd465267657def86846b259 (patch) | |
| tree | a0e6b31ff0fb94e54260a078900144a30b20804f /frontends/verilog/verilog_frontend.cc | |
| parent | 0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1 (diff) | |
| parent | 1d148491c5a9b816297c08e5ea3a98ff0bd3623d (diff) | |
| download | yosys-ec3faa7b967564dabdd465267657def86846b259.tar.gz yosys-ec3faa7b967564dabdd465267657def86846b259.tar.bz2 yosys-ec3faa7b967564dabdd465267657def86846b259.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 0e2bead6f..058d750c3 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -553,6 +553,12 @@ struct VerilogDefines : public Pass { log(" -Uname[=definition]\n"); log(" undefine the preprocessor symbol 'name'\n"); log("\n"); + log(" -reset\n"); + log(" clear list of defined preprocessor symbols\n"); + log("\n"); + log(" -list\n"); + log(" list currently defined preprocessor symbols\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -588,6 +594,16 @@ struct VerilogDefines : public Pass { design->verilog_defines.erase(name); continue; } + if (arg == "-reset") { + design->verilog_defines.clear(); + continue; + } + if (arg == "-list") { + for (auto &it : design->verilog_defines) { + log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str()); + } + continue; + } break; } |