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| author | William D. Jones <thor0505@comcast.net> | 2018-06-27 16:26:36 -0400 |
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| committer | William D. Jones <thor0505@comcast.net> | 2018-06-27 16:26:36 -0400 |
| commit | ee7164b87902313fe7a4af616891340b449db900 (patch) | |
| tree | 35226a42d64108e5ce7315976c5b088769d20ef1 /frontends/verilog/verilog_frontend.cc | |
| parent | 848c3c5c889945f64ddefc8fe45342a4338dc769 (diff) | |
| download | yosys-ee7164b87902313fe7a4af616891340b449db900.tar.gz yosys-ee7164b87902313fe7a4af616891340b449db900.tar.bz2 yosys-ee7164b87902313fe7a4af616891340b449db900.zip | |
Use msys2-provided pthreads instead of abc's.
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
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