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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:49:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 14:49:18 -0700 |
| commit | 42a6e0b0b96208c5b0d79da5d8e31e9306a8aeae (patch) | |
| tree | 7424614f63ebff3d26712b8f9d947f68f6411d9e /frontends/verilog/verilog_frontend.h | |
| parent | caec7f9d2c87e3978c51d0a4171b24cc4b363885 (diff) | |
| parent | d38f0c1a96c036df4ef67ad2f945dd229e1c3b8e (diff) | |
| download | yosys-42a6e0b0b96208c5b0d79da5d8e31e9306a8aeae.tar.gz yosys-42a6e0b0b96208c5b0d79da5d8e31e9306a8aeae.tar.bz2 yosys-42a6e0b0b96208c5b0d79da5d8e31e9306a8aeae.zip | |
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
Diffstat (limited to 'frontends/verilog/verilog_frontend.h')
| -rw-r--r-- | frontends/verilog/verilog_frontend.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index b5cf70c57..ca40946cb 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -69,11 +69,14 @@ namespace VERILOG_FRONTEND // running in -assert-assumes mode extern bool assert_assumes_mode; + // running in -noblackbox mode + extern bool noblackbox_mode; + // running in -lib mode extern bool lib_mode; - // running in -wb mode - extern bool wb_mode; + // running in -nowb mode + extern bool nowb_mode; // lexer input stream extern std::istream *lexin; |