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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-06 20:57:15 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-06 20:57:15 +0200 |
| commit | 752553d8e91643228714e04d9887d32f5d47870a (patch) | |
| tree | e7e427b9e6558800b6131022c880af8ccc053845 /frontends/verilog/verilog_frontend.h | |
| parent | 1706798f4e595266a8758ae6d0ff9d978299de10 (diff) | |
| parent | 8c6e94d57c430fc516dbcfbde312dbd7c860477b (diff) | |
| download | yosys-752553d8e91643228714e04d9887d32f5d47870a.tar.gz yosys-752553d8e91643228714e04d9887d32f5d47870a.tar.bz2 yosys-752553d8e91643228714e04d9887d32f5d47870a.zip | |
Merge pull request #946 from YosysHQ/clifford/specify
Add specify parser
Diffstat (limited to 'frontends/verilog/verilog_frontend.h')
| -rw-r--r-- | frontends/verilog/verilog_frontend.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index ca40946cb..a7c9b2fe6 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -69,14 +69,11 @@ namespace VERILOG_FRONTEND // running in -assert-assumes mode extern bool assert_assumes_mode; - // running in -noblackbox mode - extern bool noblackbox_mode; - // running in -lib mode extern bool lib_mode; - // running in -nowb mode - extern bool nowb_mode; + // running in -specify mode + extern bool specify_mode; // lexer input stream extern std::istream *lexin; |