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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-20 01:49:37 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-20 01:49:37 +0100 |
| commit | e340532ce5d60129fbfb2e1b0a3eb916ec856b26 (patch) | |
| tree | 5aed3e9da1417ba879fd8543290133deacf46e54 /frontends/verilog/verilog_frontend.h | |
| parent | a1353ec61b00442bb5ebe9f30408324b89cf6a82 (diff) | |
| download | yosys-e340532ce5d60129fbfb2e1b0a3eb916ec856b26.tar.gz yosys-e340532ce5d60129fbfb2e1b0a3eb916ec856b26.tar.bz2 yosys-e340532ce5d60129fbfb2e1b0a3eb916ec856b26.zip | |
Added init= attribute for fpga-style reset values
Diffstat (limited to 'frontends/verilog/verilog_frontend.h')
0 files changed, 0 insertions, 0 deletions