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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-15 14:57:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-15 14:57:28 +0200 |
| commit | 1d83854d84b7a0a23ee14b72c1a289b50becdeca (patch) | |
| tree | 443eb4c608d49541e461fd45f825bf93a36aea71 /frontends/verilog/verilog_lexer.l | |
| parent | 5dd3e93e8f23015d23915ee88f6ffec56166494a (diff) | |
| download | yosys-1d83854d84b7a0a23ee14b72c1a289b50becdeca.tar.gz yosys-1d83854d84b7a0a23ee14b72c1a289b50becdeca.tar.bz2 yosys-1d83854d84b7a0a23ee14b72c1a289b50becdeca.zip | |
Bugfixes in handling of "keep" attribute on wires
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
0 files changed, 0 insertions, 0 deletions