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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-01 01:29:49 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-01 16:51:24 +0200 |
| commit | 4451f7f5e9b451a7885259554cd3e9562bbf8f88 (patch) | |
| tree | 8438277a7fe0b09afe013f03b6653afd8e2a79ca /frontends/verilog/verilog_lexer.l | |
| parent | 12db9b4273cf2725f361c5fc56f768ad694f9650 (diff) | |
| download | yosys-4451f7f5e9b451a7885259554cd3e9562bbf8f88.tar.gz yosys-4451f7f5e9b451a7885259554cd3e9562bbf8f88.tar.bz2 yosys-4451f7f5e9b451a7885259554cd3e9562bbf8f88.zip | |
memory_bram: Some refactoring
This will make more sense when the new transparency masks land.
Fixes #2902.
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
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