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| author | whitequark <whitequark@whitequark.org> | 2021-07-15 22:27:27 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2021-07-15 22:27:27 +0000 |
| commit | 54b6cb645fe7ecd492521dd05072baf9086ebdb1 (patch) | |
| tree | 09294ba1b8809fbd77756206352ea23e4b864dde /frontends/verilog/verilog_lexer.l | |
| parent | 1aab608cffa19332dc5cf722def7413b16f5ee54 (diff) | |
| download | yosys-54b6cb645fe7ecd492521dd05072baf9086ebdb1.tar.gz yosys-54b6cb645fe7ecd492521dd05072baf9086ebdb1.tar.bz2 yosys-54b6cb645fe7ecd492521dd05072baf9086ebdb1.zip | |
cxxrtl: mark dead local wires as unused even with inlining disabled.
Fixes #2739.
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
0 files changed, 0 insertions, 0 deletions