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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-30 14:17:36 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-30 14:17:36 +0200 |
| commit | 7f0548c16f64bd0c4e3bd85744cfdcf9494b4829 (patch) | |
| tree | 9ca6fdebbd47f6793edace0106805a6c7235c37a /frontends/verilog/verilog_lexer.l | |
| parent | 7fecc3c199e6cfe4b474431d54027d699bc8d343 (diff) | |
| download | yosys-7f0548c16f64bd0c4e3bd85744cfdcf9494b4829.tar.gz yosys-7f0548c16f64bd0c4e3bd85744cfdcf9494b4829.tar.bz2 yosys-7f0548c16f64bd0c4e3bd85744cfdcf9494b4829.zip | |
Update examples/cmos/counter.ys to use "synth" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
0 files changed, 0 insertions, 0 deletions