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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-15 12:53:12 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-15 12:53:12 +0100 |
| commit | a588a4a5c95d14e62678c98b14af139903980be3 (patch) | |
| tree | 10a0ec49e5e637f73077e81f9d7b0e602e85374f /frontends/verilog/verilog_lexer.l | |
| parent | 8e8e791fb5dba3eb0a236cbed8c13bd5ac5ce96c (diff) | |
| download | yosys-a588a4a5c95d14e62678c98b14af139903980be3.tar.gz yosys-a588a4a5c95d14e62678c98b14af139903980be3.tar.bz2 yosys-a588a4a5c95d14e62678c98b14af139903980be3.zip | |
Fixed handling of "input foo; reg [0:0] foo;"
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
0 files changed, 0 insertions, 0 deletions