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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-08 11:50:10 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-08 11:50:10 +0100 |
| commit | b06f547993818224ded59c555345140199f4595f (patch) | |
| tree | 106dbeef7c2b70b48b40313336e0893b898d98e8 /frontends/verilog/verilog_lexer.l | |
| parent | d186ea7a2d74f859972746e03996e9eddc6a5157 (diff) | |
| download | yosys-b06f547993818224ded59c555345140199f4595f.tar.gz yosys-b06f547993818224ded59c555345140199f4595f.tar.bz2 yosys-b06f547993818224ded59c555345140199f4595f.zip | |
If direction NONE use that from first bit
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
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