diff options
| author | whitequark <whitequark@whitequark.org> | 2021-07-16 09:51:15 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2021-07-16 09:51:52 +0000 |
| commit | b28ca7f5accccae869aab1852c5b680147b3614b (patch) | |
| tree | 7313b9b01c13243a65ff6af228396a0f6ccc5f38 /frontends/verilog/verilog_lexer.l | |
| parent | 10c3214e566d8c763a68b7b18317171b707caca4 (diff) | |
| download | yosys-b28ca7f5accccae869aab1852c5b680147b3614b.tar.gz yosys-b28ca7f5accccae869aab1852c5b680147b3614b.tar.bz2 yosys-b28ca7f5accccae869aab1852c5b680147b3614b.zip | |
cxxrtl: don't expect user cell inputs to be wires.
Ports can be connected to constants, too. (Usually resets.)
Fixes #2521.
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
0 files changed, 0 insertions, 0 deletions