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| author | Clifford Wolf <clifford@clifford.at> | 2018-09-23 10:32:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-09-23 10:32:54 +0200 |
| commit | eb452ffb2861ceac572a4bef6dddb8db3b79deb7 (patch) | |
| tree | f7d7c63ef13ce3d9af9a87fdd86f3e95ffa89c19 /frontends/verilog/verilog_lexer.l | |
| parent | 9659f7a99effda1bb699f3843d3819f248c05bd0 (diff) | |
| download | yosys-eb452ffb2861ceac572a4bef6dddb8db3b79deb7.tar.gz yosys-eb452ffb2861ceac572a4bef6dddb8db3b79deb7.tar.bz2 yosys-eb452ffb2861ceac572a4bef6dddb8db3b79deb7.zip | |
Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
0 files changed, 0 insertions, 0 deletions