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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 10:34:10 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 10:34:10 -0800 |
| commit | f443695a38fbdd8c2ca38cab45ca964a173dc158 (patch) | |
| tree | 4ac13e4fe8ee5e71f963c4230f9f26f32901c2ba /frontends/verilog/verilog_lexer.l | |
| parent | d730bba6d2847515795c32d3a753320b8b48bee0 (diff) | |
| parent | da6abc014987ef562a577dc374bcb03aad9256cd (diff) | |
| download | yosys-f443695a38fbdd8c2ca38cab45ca964a173dc158.tar.gz yosys-f443695a38fbdd8c2ca38cab45ca964a173dc158.tar.bz2 yosys-f443695a38fbdd8c2ca38cab45ca964a173dc158.zip | |
Merge remote-tracking branch 'origin/master' into eddie/verific_help
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 4acfb414d..ca23df3e8 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -28,7 +28,7 @@ * * A simple lexer for Verilog code. Non-preprocessor compiler directives are * handled here. The preprocessor stuff is handled in preproc.cc. Everything - * else is left to the bison parser (see parser.y). + * else is left to the bison parser (see verilog_parser.y). * */ @@ -188,9 +188,9 @@ YOSYS_NAMESPACE_END "unique0" { SV_KEYWORD(TOK_UNIQUE); } "priority" { SV_KEYWORD(TOK_PRIORITY); } -"always_comb" { SV_KEYWORD(TOK_ALWAYS); } -"always_ff" { SV_KEYWORD(TOK_ALWAYS); } -"always_latch" { SV_KEYWORD(TOK_ALWAYS); } +"always_comb" { SV_KEYWORD(TOK_ALWAYS_COMB); } +"always_ff" { SV_KEYWORD(TOK_ALWAYS_FF); } +"always_latch" { SV_KEYWORD(TOK_ALWAYS_LATCH); } /* use special token for labels on assert, assume, cover, and restrict because it's insanley complex to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some |