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| author | Zachary Snow <zach@zachjs.com> | 2021-01-21 08:30:55 -0700 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-01-21 08:42:05 -0700 |
| commit | 1096b969efb24dc28b501585f23ceb242d781745 (patch) | |
| tree | 2d887c1512458456391bb6c098f2dc2eba46db90 /frontends/verilog/verilog_parser.y | |
| parent | 699a98b265a41b0565637323f929e6cb1f8837e0 (diff) | |
| download | yosys-1096b969efb24dc28b501585f23ceb242d781745.tar.gz yosys-1096b969efb24dc28b501585f23ceb242d781745.tar.bz2 yosys-1096b969efb24dc28b501585f23ceb242d781745.zip | |
Allow combination of rand and const modifiers
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 2886db0e5..8bd58d24c 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -651,8 +651,16 @@ wire_type_signedness: %empty; wire_type_const_rand: - TOK_CONST { current_wire_const = true; } | - TOK_RAND { current_wire_rand = true; } | + TOK_RAND TOK_CONST { + current_wire_rand = true; + current_wire_const = true; + } | + TOK_CONST { + current_wire_const = true; + } | + TOK_RAND { + current_wire_rand = true; + } | %empty; opt_wire_type_token: |