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| author | Tim Ansell <me@mith.ro> | 2018-10-04 17:15:30 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2018-10-08 11:38:10 -0700 |
| commit | 3661c27acda1b011f2e82c2656e3a701bb63ded6 (patch) | |
| tree | 8d14fc39a3968bac1625f6fe065a47c12b142286 /frontends/verilog/verilog_parser.y | |
| parent | 81d77c4911ed1d660fa6f72f4bde48046aae776b (diff) | |
| download | yosys-3661c27acda1b011f2e82c2656e3a701bb63ded6.tar.gz yosys-3661c27acda1b011f2e82c2656e3a701bb63ded6.tar.bz2 yosys-3661c27acda1b011f2e82c2656e3a701bb63ded6.zip | |
Fix misspelling in issue_template.md
It's been bugging me :-P
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
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