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| author | Marcus Comstedt <marcus@mc.pp.se> | 2015-11-08 19:16:56 +0100 |
|---|---|---|
| committer | Marcus Comstedt <marcus@mc.pp.se> | 2015-11-08 19:16:56 +0100 |
| commit | 8c2bdef36dbdb5b830757a4f74a7600b45828698 (patch) | |
| tree | 24ff88378d93bba90017406845c6e91010cbb2de /frontends/verilog/verilog_parser.y | |
| parent | 1ec6429bad4d793b389ee594b1cb2575bf73ddaf (diff) | |
| download | yosys-8c2bdef36dbdb5b830757a4f74a7600b45828698.tar.gz yosys-8c2bdef36dbdb5b830757a4f74a7600b45828698.tar.bz2 yosys-8c2bdef36dbdb5b830757a4f74a7600b45828698.zip | |
Fix a segfault in dffinit when the value has too few bits
The code was already trying to add the required number of bits, but
fell one short of the mark.
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
0 files changed, 0 insertions, 0 deletions