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author | Zachary Snow <zach@zachjs.com> | 2021-02-11 10:26:06 -0500 |
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committer | GitHub <noreply@github.com> | 2021-02-11 10:26:06 -0500 |
commit | c383d156e9015cde4718f3a6bc3371dc87c3e4fe (patch) | |
tree | 56859d2a50896707bd20c11619e19de8736b32d4 /frontends/verilog/verilog_parser.y | |
parent | eff18a2b1519428b11400979f116342086c13e13 (diff) | |
parent | 75335344295a51c11bb72e0add10e365a34ccc1d (diff) | |
download | yosys-c383d156e9015cde4718f3a6bc3371dc87c3e4fe.tar.gz yosys-c383d156e9015cde4718f3a6bc3371dc87c3e4fe.tar.bz2 yosys-c383d156e9015cde4718f3a6bc3371dc87c3e4fe.zip |
Merge pull request #2584 from antmicro/atom_type_signedness
verilog_parser: fix missing is_signed attribute in type_atom
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
-rw-r--r-- | frontends/verilog/verilog_parser.y | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index fb5846f7b..69fd66cba 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1491,10 +1491,10 @@ enum_base_type: type_atom type_signing | %empty { astbuf1->is_reg = true; addRange(astbuf1); } ; -type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed - | TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed - | TOK_SHORTINT { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); } // 2-state signed - | TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed +type_atom: TOK_INTEGER { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1); } // 4-state signed + | TOK_INT { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1); } // 2-state signed + | TOK_SHORTINT { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1, 15, 0); } // 2-state signed + | TOK_BYTE { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1, 7, 0); } // 2-state signed ; type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned |