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| author | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-27 12:11:47 +0200 |
|---|---|---|
| committer | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-27 12:11:47 +0200 |
| commit | 0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7 (patch) | |
| tree | 9ed03b8345847046143161c3a63b8fa599393da2 /frontends/verilog | |
| parent | 2454ad99bf49afe752d6fd1c1567f59ee9e26736 (diff) | |
| parent | 0d2b87e3ed9bacae7d44d27a4712e56ca03c8dd3 (diff) | |
| download | yosys-0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7.tar.gz yosys-0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7.tar.bz2 yosys-0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/const2ast.cc | 14 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 |
2 files changed, 8 insertions, 7 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 57d366dbf..f6a17b242 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -153,7 +153,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn { if (warn_z) { AstNode *ret = const2ast(code, case_type); - if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) + if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n", current_filename.c_str(), get_line_num()); return ret; @@ -204,7 +204,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn { std::vector<RTLIL::State> data; bool is_signed = false; - bool is_unsized = false; + bool is_unsized = len_in_bits < 0; if (*(endptr+1) == 's') { is_signed = true; endptr++; @@ -213,25 +213,25 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn { case 'b': case 'B': - my_strtobin(data, endptr+2, len_in_bits, 2, case_type, false); + my_strtobin(data, endptr+2, len_in_bits, 2, case_type, is_unsized); break; case 'o': case 'O': - my_strtobin(data, endptr+2, len_in_bits, 8, case_type, false); + my_strtobin(data, endptr+2, len_in_bits, 8, case_type, is_unsized); break; case 'd': case 'D': - my_strtobin(data, endptr+2, len_in_bits, 10, case_type, false); + my_strtobin(data, endptr+2, len_in_bits, 10, case_type, is_unsized); break; case 'h': case 'H': - my_strtobin(data, endptr+2, len_in_bits, 16, case_type, false); + my_strtobin(data, endptr+2, len_in_bits, 16, case_type, is_unsized); break; default: char next_char = char(tolower(*(endptr+1))); if (next_char == '0' || next_char == '1' || next_char == 'x' || next_char == 'z') { - my_strtobin(data, endptr+1, 1, 2, case_type, true); is_unsized = true; + my_strtobin(data, endptr+1, 1, 2, case_type, is_unsized); } else { return NULL; } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4895d0302..d89b2dc88 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -517,6 +517,7 @@ wire_type_token: TOK_GENVAR { astbuf3->type = AST_GENVAR; astbuf3->is_reg = true; + astbuf3->is_signed = true; astbuf3->range_left = 31; astbuf3->range_right = 0; } | |