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| author | David Shah <dave@ds0.me> | 2020-02-02 14:53:32 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-02 14:53:32 +0000 |
| commit | 1055b6b1dd7e4a557b33f6dc4bb14b09dcd582dc (patch) | |
| tree | 7d1ce26e6d48109f573a5f0e99bb03af42f12bc9 /frontends/verilog | |
| parent | b44d0e041f09216dd90dccd3f18f146b1dfb7e92 (diff) | |
| parent | 65716c998272704c057d846076dc3258c74f5a34 (diff) | |
| download | yosys-1055b6b1dd7e4a557b33f6dc4bb14b09dcd582dc.tar.gz yosys-1055b6b1dd7e4a557b33f6dc4bb14b09dcd582dc.tar.bz2 yosys-1055b6b1dd7e4a557b33f6dc4bb14b09dcd582dc.zip | |
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
synth_xilinx: add -dsp-multonly
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions