diff options
| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-17 06:16:59 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-17 06:16:59 +0000 |
| commit | 10a814f97808de8cce7e50a03f01832db66c263e (patch) | |
| tree | 44afa7d32f1137ebfe1a2f7048fdc4c28579ba8f /frontends/verilog | |
| parent | c69db910acef73bbd5a1bfb015231fce5419e0af (diff) | |
| download | yosys-10a814f97808de8cce7e50a03f01832db66c263e.tar.gz yosys-10a814f97808de8cce7e50a03f01832db66c263e.tar.bz2 yosys-10a814f97808de8cce7e50a03f01832db66c263e.zip | |
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 7447ab8d5..f762f9025 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1924,11 +1924,13 @@ always_events: always_event: TOK_POSEDGE expr { AstNode *node = new AstNode(AST_POSEDGE); + SET_AST_NODE_LOC(node, @1, @1); ast_stack.back()->children.push_back(node); node->children.push_back($2); } | TOK_NEGEDGE expr { AstNode *node = new AstNode(AST_NEGEDGE); + SET_AST_NODE_LOC(node, @1, @1); ast_stack.back()->children.push_back(node); node->children.push_back($2); } | |