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| author | whitequark <whitequark@whitequark.org> | 2021-07-16 08:33:30 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-16 08:33:30 +0000 |
| commit | 10c3214e566d8c763a68b7b18317171b707caca4 (patch) | |
| tree | 7fa68e74d99b7d1d91ba7dd41b780832e9251702 /frontends/verilog | |
| parent | c17e385e3563e918e87a4f8bafbe290dd0911a8b (diff) | |
| parent | 44a3d924ce30adfd3a09ffea40031a8d28445e25 (diff) | |
| download | yosys-10c3214e566d8c763a68b7b18317171b707caca4.tar.gz yosys-10c3214e566d8c763a68b7b18317171b707caca4.tar.bz2 yosys-10c3214e566d8c763a68b7b18317171b707caca4.zip | |
Merge pull request #2871 from whitequark/cxxrtl-fix-2540-2841
cxxrtl: don't mark buffered internal wires as UNUSED for debug
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions