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| author | Siesh1oo <siesh1oo@siesh1oo.no> | 2014-03-10 20:12:20 +0100 |
|---|---|---|
| committer | Siesh1oo <siesh1oo@siesh1oo.no> | 2014-03-13 11:29:03 +0100 |
| commit | 1cd7fbb6b8da3b56273426cf2fd13bec49ec0fed (patch) | |
| tree | e484c1a56d18a88fdce370e8b78d7be931b84b34 /frontends/verilog | |
| parent | cb4293624e11d61f64e51027fabc73fbcf504fa2 (diff) | |
| download | yosys-1cd7fbb6b8da3b56273426cf2fd13bec49ec0fed.tar.gz yosys-1cd7fbb6b8da3b56273426cf2fd13bec49ec0fed.tar.bz2 yosys-1cd7fbb6b8da3b56273426cf2fd13bec49ec0fed.zip | |
- Makefile: fix typo in LDFLAGS: obviously -L, not -I is required here
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions