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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-30 10:03:54 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-30 10:04:26 +0200 |
| commit | 2faa1d0e80d213461d4403e36499aaaf1c8088b8 (patch) | |
| tree | e0d83c14f7030015ace263a991f44ceaa1e3a4e8 /frontends/verilog | |
| parent | 0df8a3b461a0d56725a32d397d0f8a041eedc191 (diff) | |
| download | yosys-2faa1d0e80d213461d4403e36499aaaf1c8088b8.tar.gz yosys-2faa1d0e80d213461d4403e36499aaaf1c8088b8.tar.bz2 yosys-2faa1d0e80d213461d4403e36499aaaf1c8088b8.zip | |
Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions