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| author | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2020-02-03 10:56:11 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2020-02-03 10:56:41 -0300 |
| commit | 313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc (patch) | |
| tree | f35f8834f0cc30380c32d5ed3a38cb2673304931 /frontends/verilog | |
| parent | 71f3afb9a26e7bad2a9e9d59877a94cbd757cad4 (diff) | |
| parent | 7033503cd9e40e16c11fe6c805a436b0e23989dd (diff) | |
| download | yosys-313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc.tar.gz yosys-313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc.tar.bz2 yosys-313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys
Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index ca23df3e8..9b43c250e 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -431,6 +431,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { "+:" { return TOK_POS_INDEXED; } "-:" { return TOK_NEG_INDEXED; } +".*" { return TOK_WILDCARD_CONNECT; } + [-+]?[=*]> { if (!specify_mode) REJECT; frontend_verilog_yylval.string = new std::string(yytext); diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index a30935e0a..2c7304cc4 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -138,7 +138,7 @@ struct specify_rise_fall { %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP -%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR +%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH @@ -1580,6 +1580,11 @@ cell_port: node->children.back()->str = *$3; delete $3; free_attr($1); + } | + attr TOK_WILDCARD_CONNECT { + if (!sv_mode) + frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode."); + astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false); }; always_comb_or_latch: |