diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:48:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:48:45 -0700 |
| commit | 4c9fde87d170fc8d4b729581b055407553951e4c (patch) | |
| tree | 6213f8f04492f2868737a4a8348abfd07e0f7c80 /frontends/verilog | |
| parent | 2dffa4685b830313204f5d04314a14ed6ecac8ec (diff) | |
| download | yosys-4c9fde87d170fc8d4b729581b055407553951e4c.tar.gz yosys-4c9fde87d170fc8d4b729581b055407553951e4c.tar.bz2 yosys-4c9fde87d170fc8d4b729581b055407553951e4c.zip | |
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec.
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 9558bbfb9..3c612472d 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -311,6 +311,11 @@ supply1 { return TOK_SUPPLY1; } return TOK_ID; } +"$"(info|warning|error|fatal) { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_ELAB_TASK; +} + "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } |