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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 20:02:19 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 20:02:19 -0700 |
| commit | 4de25a1949c14f4c343eae957b9402b5ddb574c9 (patch) | |
| tree | d23c3971982bf21b4b5bbef58fd45f1c3b339ab8 /frontends/verilog | |
| parent | a7a88109f5b750862b8e45c194e8094fd32b8a5f (diff) | |
| download | yosys-4de25a1949c14f4c343eae957b9402b5ddb574c9.tar.gz yosys-4de25a1949c14f4c343eae957b9402b5ddb574c9.tar.bz2 yosys-4de25a1949c14f4c343eae957b9402b5ddb574c9.zip | |
Add WE to ECP5 dist RAM's abc_scc_break too
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