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| author | Claire Xen <claire@clairexen.net> | 2021-06-09 13:22:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-09 13:22:52 +0200 |
| commit | 55e8f5061af57bf25bd9e30528de8196c6eabe9e (patch) | |
| tree | e4fcc0a71494dd1023e938b2ed041489c7536014 /frontends/verilog | |
| parent | 2e697f5655455fd8ce5fec40b94683a11ade24e8 (diff) | |
| parent | 588137cd082849cfa3dee92a01ac4ee91f6ed946 (diff) | |
| download | yosys-55e8f5061af57bf25bd9e30528de8196c6eabe9e.tar.gz yosys-55e8f5061af57bf25bd9e30528de8196c6eabe9e.tar.bz2 yosys-55e8f5061af57bf25bd9e30528de8196c6eabe9e.zip | |
Merge pull request #2817 from YosysHQ/claire/fixemails
Fixing old e-mail addresses and deadnames
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/const2ast.cc | 2 | ||||
| -rw-r--r-- | frontends/verilog/preproc.cc | 2 | ||||
| -rw-r--r-- | frontends/verilog/preproc.h | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_frontend.h | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
7 files changed, 7 insertions, 7 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 230dfadbf..a4dfbc7ec 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 568224da2..4b9ebe0aa 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/frontends/verilog/preproc.h b/frontends/verilog/preproc.h index 673d633c0..e1048156c 100644 --- a/frontends/verilog/preproc.h +++ b/frontends/verilog/preproc.h @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 84ac73e91..ad0bb9ff7 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index aa7881038..30f1c1180 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index f52928c77..b29e625d6 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 93ddbec91..10d904dbd 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above |