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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-02 10:44:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-02 10:44:59 -0700 |
| commit | 5cd19b52da297cc7d44e9bf11dc9d1664a02ccce (patch) | |
| tree | 6206a4fa059c47a56cc43914d4141a386a5f2c7f /frontends/verilog | |
| parent | 4aca928033874e8e35ecc4a18f22475c00bebad9 (diff) | |
| parent | 98925f6c4be611434e75f0ccf645a7ef8adcfc63 (diff) | |
| download | yosys-5cd19b52da297cc7d44e9bf11dc9d1664a02ccce.tar.gz yosys-5cd19b52da297cc7d44e9bf11dc9d1664a02ccce.tar.bz2 yosys-5cd19b52da297cc7d44e9bf11dc9d1664a02ccce.zip | |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index ed6ce2ecb..9e624d355 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -242,8 +242,6 @@ struct VerilogFrontend : public Frontend { nowb_mode = false; default_nettype_wire = true; - log_header(design, "Executing Verilog-2005 frontend.\n"); - args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); size_t argidx; @@ -415,6 +413,8 @@ struct VerilogFrontend : public Frontend { } extra_args(f, filename, args, argidx); + log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str()); + log("Parsing %s%s input from `%s' to AST representation.\n", formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); |