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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-02 09:58:20 -0800 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-02 09:58:20 -0800 |
| commit | 5d93dcce862d281f0df495eeee755cd4bfca342d (patch) | |
| tree | 4783ecac57c91caeb28a14f22c1b011c7d4cf283 /frontends/verilog | |
| parent | f2f5ecd83468fc94bf1ec8d72734fa531d0b2b32 (diff) | |
| download | yosys-5d93dcce862d281f0df495eeee755cd4bfca342d.tar.gz yosys-5d93dcce862d281f0df495eeee755cd4bfca342d.tar.bz2 yosys-5d93dcce862d281f0df495eeee755cd4bfca342d.zip | |
Fix $readmem[hb] for mem2reg memories, fixes #785
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions