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| author | David Shah <dave@ds0.me> | 2019-11-22 09:04:54 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-02-02 16:12:33 +0000 |
| commit | 5df591c02309c086229029808c21ab8721278888 (patch) | |
| tree | 0405b135a313ebb1da7a6d1597f670b3f2582e26 /frontends/verilog | |
| parent | 50f86c11b2bb9e561f5a0cf10e053b1aa4918abd (diff) | |
| download | yosys-5df591c02309c086229029808c21ab8721278888.tar.gz yosys-5df591c02309c086229029808c21ab8721278888.tar.bz2 yosys-5df591c02309c086229029808c21ab8721278888.zip | |
hierarchy: Resolve SV wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index cb413e13a..5ec8e66a6 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1582,7 +1582,7 @@ cell_port: free_attr($1); } | attr TOK_AUTOCONNECT_ALL { - astbuf2->attributes[ID(autoconnect)] = AstNode::mkconst_int(1, false); + astbuf2->attributes[ID(implicit_port_conns)] = AstNode::mkconst_int(1, false); }; always_comb_or_latch: |