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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-09-11 17:18:26 -0700 |
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| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-09-12 18:47:46 -0700 |
| commit | 6da5d36968b2792e27291adb1c89f0b1db5c5cd0 (patch) | |
| tree | f9b8a0fd9e7fd8add928a47588c07e89607fe744 /frontends/verilog | |
| parent | f9d023c53fedd96ec1b9d3a93d0448291a1f2527 (diff) | |
| download | yosys-6da5d36968b2792e27291adb1c89f0b1db5c5cd0.tar.gz yosys-6da5d36968b2792e27291adb1c89f0b1db5c5cd0.tar.bz2 yosys-6da5d36968b2792e27291adb1c89f0b1db5c5cd0.zip | |
Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved
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