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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-04 21:58:25 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-04 21:58:25 +0200 |
| commit | 70d0f389ad6e7e0ad762b62d3a626a4db5b23827 (patch) | |
| tree | 285b758efa19342a8e136772190d55672329cba2 /frontends/verilog | |
| parent | a01386c0e45b4eee5295db440740a1ab271396fe (diff) | |
| parent | 9804c86e87ec83edd29d224f01311b6ae1d41181 (diff) | |
| download | yosys-70d0f389ad6e7e0ad762b62d3a626a4db5b23827.tar.gz yosys-70d0f389ad6e7e0ad762b62d3a626a4db5b23827.tar.bz2 yosys-70d0f389ad6e7e0ad762b62d3a626a4db5b23827.zip | |
Merge pull request #988 from YosysHQ/clifford/fix987
Add approximate support for SV "var" keyword
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 1 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 5 |
2 files changed, 5 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index e97632663..08e556e8e 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -208,6 +208,7 @@ YOSYS_NAMESPACE_END "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); } "final" { SV_KEYWORD(TOK_FINAL); } "logic" { SV_KEYWORD(TOK_LOGIC); } +"var" { SV_KEYWORD(TOK_VAR); } "bit" { SV_KEYWORD(TOK_REG); } "eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 9edb61a39..08377ad9a 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -110,7 +110,7 @@ static void free_attr(std::map<std::string, AstNode*> *al) %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP -%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT +%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT @@ -456,6 +456,9 @@ wire_type_token: TOK_LOGIC { astbuf3->is_logic = true; } | + TOK_VAR { + astbuf3->is_logic = true; + } | TOK_INTEGER { astbuf3->is_reg = true; astbuf3->range_left = 31; |