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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-23 19:18:45 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-23 19:18:45 +0200 |
| commit | 7703be045a0a46ed70ec19b5db731e33fa56cef5 (patch) | |
| tree | 9fc7b58e713c9c18f205a2ec944de6fdd41bd411 /frontends/verilog | |
| parent | 23b69ca32b2ef93fc4b3f724099bfecdee0af869 (diff) | |
| parent | b65932edc4a00860cafc04f962f2a08dd782b075 (diff) | |
| download | yosys-7703be045a0a46ed70ec19b5db731e33fa56cef5.tar.gz yosys-7703be045a0a46ed70ec19b5db731e33fa56cef5.tar.bz2 yosys-7703be045a0a46ed70ec19b5db731e33fa56cef5.zip | |
Merge pull request #677 from daveshah1/ecp5_dsp
ecp5: Add blackboxes for MULT18X18D and ALU54B
Diffstat (limited to 'frontends/verilog')
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