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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-23 14:41:41 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-23 14:41:41 +0200 |
| commit | 92c2a04e19e1fc27732208f02ced93ebca447612 (patch) | |
| tree | 6009afca8f1bc2257770d877c56cfbe449e6e328 /frontends/verilog | |
| parent | 408077769ff022f78f10ec1ffb60926361f8dc9f (diff) | |
| parent | 042b3074f8096212b3f2114d353b2ec75818810b (diff) | |
| download | yosys-92c2a04e19e1fc27732208f02ced93ebca447612.tar.gz yosys-92c2a04e19e1fc27732208f02ced93ebca447612.tar.bz2 yosys-92c2a04e19e1fc27732208f02ced93ebca447612.zip | |
Merge pull request #614 from udif/pr_disable_dump_ptr
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 911e36112..8dcc7c5aa 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -78,6 +78,9 @@ struct VerilogFrontend : public Frontend { log(" -dump_ast2\n"); log(" dump abstract syntax tree (after simplification)\n"); log("\n"); + log(" -no_dump_ptr\n"); + log(" do not include hex memory addresses in dump (easier to diff dumps)\n"); + log("\n"); log(" -dump_vlog\n"); log(" dump ast as Verilog code (after simplification)\n"); log("\n"); @@ -184,6 +187,7 @@ struct VerilogFrontend : public Frontend { { bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; + bool flag_no_dump_ptr = false; bool flag_dump_vlog = false; bool flag_dump_rtlil = false; bool flag_nolatches = false; @@ -241,6 +245,10 @@ struct VerilogFrontend : public Frontend { flag_dump_ast2 = true; continue; } + if (arg == "-no_dump_ptr") { + flag_no_dump_ptr = true; + continue; + } if (arg == "-dump_vlog") { flag_dump_vlog = true; continue; @@ -381,7 +389,7 @@ struct VerilogFrontend : public Frontend { if (flag_nodpi) error_on_dpi_function(current_ast); - AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); + AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; |